1. Field of the Invention
The present invention relates to signal potential conversion circuits. In particular, the invention relates to a signal potential conversion circuit converting a first signal having one level of a first potential and the other level of a reference potential into a second signal hating one level of a second potential different from the first potential and the other level of the reference potential.
2. Description of the Background Art
A semiconductor integrated circuit device has been provided with a signal potential conversion circuit for converting a signal potential into another signal potential. For example, a dynamic random access memory (hereinafter referred to as DRAM) has memory cells each including an N channel MOS transistor for access and a capacitor for information storage. Data of xe2x80x9cHxe2x80x9d (logical high) level (power supply potential VDD) or xe2x80x9cLxe2x80x9d (logical low) level (ground potential GND) is written into the capacitor. Data is written into/read from the capacitor via the N channel MOS transistor. In data writing/reading, for the purpose of preventing voltage drop in the N channel MOS transistor, a boosted potential (VPP) higher than the supply potential VDD is applied to the gate of the N channel MOS transistor. Peripheral control circuitry for writing/reading of data is driven by the supply voltage VDD. Therefore, in order to transmit a signal from the peripheral control circuitry to a memory cell, a signal potential conversion circuit is required to convert the supply potential VDD into the boosted potential VPP.
FIG. 10 is a circuit diagram showing a structure of such a signal potential conversion circuit. Referring to FIG. 10, the signal potential conversion circuit includes inverters 31-33, P channel MOS transistors 34 and 35, and N channel MOS transistors 36 and 37.
P channel MOS transistors 34 and 35 are connected respectively between a line of the boosted potential VPP and nodes N34 and N35, having respective gates connected to nodes N35 and N34 respectively. N channel MOS transistors 36 and 37 are connected respectively between nodes N34 and N35 and a line of the ground potential GND. An input signal VI is supplied to the gate of N channel MOS transistor 36 via inverter 31 and supplied to the gate of N channel MOS transistor 37 via inverters 31 and 32. A signal appearing on node N35 is inverted by inverter 33 and output as an output signal VO.
Inverters 31 and 32 each include a P channel MOS transistor and an N channel MOS transistor connected in series between a line of the supply potential VDD and the line of the ground potential GND, outputting a signal of L level in response to input of a signal of H level and outputting a signal of H level in response to input of a signal of L level.
Inverter 33 includes a P channel MOS transistor and an N channel MOS transistor connected in series between the line of the boosted potential VPP and the line of the ground potential GND, outputting a signal of L level in response to input of a signal of the boosted potential VPP and outputting a signal of the boosted potential VPP in response to input of a signal of L level.
FIG. 11 is a timing chart showing an operation of the signal potential conversion circuit shown in FIG. 10. In the initial state, input signal VI, an output signal xcfx8632 from inverter 32, node N34 and output signal VO are all at L level, an output signal xcfx8631 from inverter 31 is at H level and node N35 is at the boosted potential VPP. At this time, MOS transistors 35 and 36 are conductive while MOS transistors 34 and 37 are nonconductive.
When input signal VI rises from L level to H level at a certain time, signal xcfx8631 falls to L level to turn off N channel MOS transistor 36 and signal xcfx8632 rises to H level to turn on N channel MOS transistor 37. Accordingly, the potential on node N35 gradually decreases. When this potential becomes lower than VPPxe2x88x92|Vthp| (Vthp is the threshold voltage of the P channel MOS transistor), P channel MOS transistor 34 is turned on and node N34 rises to the boosted potential VPP. When node N34 reaches the boosted potential VPP, P channel MOS transistor 35 is turned off, node N35 falls to L level, and output signal VO rises to the boosted potential VPP.
Following this, when input signal VI falls from H level to L level, signal xcfx8631 rises to H level to turn on N channel MOS transistor 36 and signal xcfx8632 falls to L level to turn off N channel MOS transistor 37. Accordingly, the potential on node N34 gradually decreases. When this potential becomes lower than VPPxe2x88x92|Vthp|, P channel MOS transistor 35 is turned on and node N35 rises to the boosted potential VPP. When node N35 reaches the boosted potential VPP, P channel MOS transistor 34 is turned off, node N34 falls to L level, and output signal VO falls to L level.
In order to achieve reduced power consumption and enhanced speed of semiconductor integrated circuit devices, reduction of a power supply voltage thereof is now proceeding. Reduction of a power supply voltage of the DRAM is also in progress. However, reduction of the voltage for circuit components related to reading/writing of data from/into a memory cell cannot be promoted because of the necessity of maintaining a high-speed operation. Consequently, the difference between the voltage level of the peripheral control circuitry and the voltage level of the circuit components related to reading/writing of a memory cell is likely to become greater so that the difference between the input voltage VDD and the output voltage VPP of the signal potential conversion circuit tends to increase.
Regarding the conventional signal potential conversion circuit, node N34 should be charged to VPPxe2x88x92|Vthp| or higher for turning off P channel MOS transistor 35 when input signal VI rises from L level to H level. If the potential difference between the boosted potential VPP and the supply potential VDD becomes greater, the off level VPPxe2x88x92|Vthp| of N channel MOS transistor N35 becomes higher and accordingly charging of node N34 to VPPxe2x88x92|Vthp| takes a longer time. In other words, a problem of the conventional signal potential conversion circuit is that the increased difference between the input voltage VDD and the output voltage VPP prolongs the time required to convert a signal potential.
Although node N34 can be charged speedily by increasing the gate width of P channel MOS transistor 34 to enhance the current drive ability of P channel MOS transistor 34, discharging of node N34 to L level takes a longer time. Therefore, regarding the conventional signal potential conversion circuit, the time required for converting a signal potential cannot be shortened for both of the cases in which input signal VI rises from L level to H level and in which input signal VI falls from H level to L level.
One object of the present invention is accordingly to provide a signal potential conversion circuit capable of converting a signal potential speedily.
According to the present invention, a signal potential conversion circuit includes a discharge circuit discharging, in response to change of a first signal from a first potential to a reference potential, a first output node to the reference potential, the first output node provided for outputting a second signal, and discharging, in response to change of the first signal from the reference potential to the first potential, a second output node to the reference potential, the second output node provided for outputting a complementary signal of the second signal. The signal potential conversion circuit further includes a charge circuit including a first transistor and a second transistor having respective first electrodes both connected to a line of a second potential, respective second electrodes connected to the first and second output nodes respectively and respective input electrodes connected to the second and first output nodes respectively, the charge circuit charging to the second potential one of the first and second output nodes having a higher potential than that of the other output node. The signal potential conversion circuit further includes a third transistor of a first conductivity type connected between the line of the second potential and the second output node, and a first control circuit turning on the third transistor in a pulse manner in response to change of the first signal from the first potential to the reference potential. In this way, when the first signal changes from the first potential to the reference potential, the third transistor is turned on in a pulse manner to enable the second output node to be charged speedily. The third transistor is not turned on when the first signal changes from the reference potential to the first potential to enable the second output node to be discharged speedily. The second transistor can thus be controlled quickly and accordingly a speedily conversion of a signal potential is possible.
Preferably, the first control circuit turns on the third transistor when the first signal has the reference potential and the first output node has a potential higher than a predetermined third potential. In this case, the third transistor is turned on when the first signal has the reference potential while the potential on the first output node is still higher than the third potential.
More preferably, the first control circuit includes a first resistance element connected between the line of the second potential and an input electrode of the third transistor, a fourth transistor of a second conductivity type having its first electrode connected to the input electrode of the third transistor and its input electrode connected to the first output node and turned on when the first output node has a potential higher than the third potential, and a fifth transistor of the second conductivity type connected between a second electrode of the fourth transistor and a line of the reference potential and turned on when the first signal has the reference potential. In this case, when the first signal has the reference potential and the first output node has its potential higher than the third potential, the fourth and fifth transistors are turned on and the third transistor with its input electrode having the reference potential is turned on.
Still more preferably, a current level which the second transistor can flow is set sufficiently lower than a current level which the discharge circuit can flow. In this case, the second output node can more speedily be discharged when the first signal changes from the reference potential to the first potential.
Still more preferably, the signal potential conversion circuit further includes a sixth transistor of the first conductivity type connected between the line of the second potential and the first output node, and a second control circuit turning on the sixth transistor in a pulse manner in response to change of the first signal from the reference potential to the first potential. In this case, the first output node can speedily be charged since the sixth transistor is turned on in a pulse manner when the first signal changes from the reference potential to the first potential. Further, the first output node can quickly be discharged since the sixth transistor is not turned on when the first signal changes from the first potential to the reference potential. In this way, the second transistor clan quickly be controlled to enable conversion of a signal potential to be accomplished more speedily.
Still more preferably, the second control circuit turns on the sixth transistor when the first signal has the first potential and the second output node has a potential higher than a predetermined third potential. In this case, the sixth transistor is turned on when the second output node has a potential between the third potential and the second potential.
Still more preferably, the second control circuit includes a second resistance element connected between the line of the second potential and an input electrode of the sixth transistor, a seventh transistor of the second conductivity type having its first electrode connected to the input electrode of the sixth transistor and its input electrode connected to the second output node and turned on when the second output node has a potential higher than the third potential, and an eighth transistor of the second conductivity type connected between a second electrode of the seventh transistor and the line of the reference potential and turned on when the first signal has the first potential. In this case, when the first signal has the first potential and the second output node has a potential higher than the third potential, the seventh and eighth transistors are turned on and the sixth transistor with its input electrode having the reference potential is turned on.
Still more preferably, the first control circuit turns on the third transistor when the first signal has the reference potential and the second output node has a potential lower than a predetermined third potential. In this case, the third transistor is turned on when the first signal has the reference potential while the second output node has a potential which is still lower than the third potential.
Still more preferably, the first control circuit includes a first resistance element connected between the line of the second potential and the input electrode of the third transistor, a fourth transistor of the second conductivity type connected between the input electrode of the third transistor and the line of the reference potential, and a first logic circuit turning on the fourth transistor when the first signal has the reference potential and the second output node has a potential lower than the third potential. In this case, when the first signal has the reference potential and the second output node has a potential lower than the third potential, the fourth transistor is turned on and the third transistor with its input electrode having the reference potential is turned on.
Still more preferably, the signal potential conversion circuit further includes a fifth transistor of the first conductivity type connected between the line of the second potential and the first output node, and a second control circuit turning on the fifth transistor in a pulse manner in response to change of the first signal from the reference potential to the first potential. In this case, the fifth transistor is turned on in a pulse manner when the first signal changes from the reference potential to the first potential so that the first output node can be charged speedily. As the fifth transistor is not turned on when the first signal changes from the first potential to the reference potential, the first output node can be discharged quickly. In this way, speedy control of the second transistor is possible and thus conversion of a signal potential can be done more quickly.
Still more preferably, the second control circuit turns on the fifth transistor when the first signal has the first potential and the first output node has a potential lower than the third potential. In this case, the fifth transistor is turned on when the first signal has the first potential while the potential on the first output node is still lower than the third potential.
Still more preferably, the second control circuit includes a second resistance element connected between the line of the second potential and an input electrode of the fifth transistor, a sixth transistor of the second conductivity type connected between the input electrode of the fifth transistor and the line of the reference potential, and a second logic circuit turning on the sixth transistor when the first signal has the first potential and the first output node has a potential lower than the third potential. In this case, when the first signal has the first potential and the potential on the first output node is lower than the third potential, the sixth transistor is turned on and the fifth transistor with its input electrode having the reference potential is turned on.
Still more preferably, a current level which the first and second transistors each can flow is set sufficiently lower than a current level which the discharge circuit can flow. In this case, discharge of the first and second output nodes can be performed more quickly.
Still more preferably, the discharge circuit includes a ninth transistor of the second conductivity type connected between the first output node and the line of the reference potential and turned on when the first signal has the level of the reference potential, and a tenth transistor of the second conductivity type connected between the second output node and the line of the reference potential and turned on when the first signal has the level of the first potential. In this case, the discharge circuit can easily be constructed.
Still more preferably, the discharge circuit includes a ninth transistor of the second conductivity type connected between the first output node and the line of the reference potential and turned on when the first signal has the level of the reference potential, and a tenth transistor of the second conductivity type having a first electrode connected to the second output node, a second electrode receiving a complementary signal of the first signal and an input electrode receiving the first potential, and turned on when the first signal has the level of the first potential. In this case, a complementary signal of the first signal can be transmitted to the second output node.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.